The present invention relates in general to field programmable gate arrays and, more particularly, to a circuit and method of configuring a field programmable gate array.
Field programmable gate arrays (FPGA) are commonly used in electronic circuit design to perform a logic function. The FPGA is enclosed in an integrated circuit (IC) package, and a number of FPGA IC packages are typically disposed on a printed circuit board. The FPGA includes an array of logic gates, e.g. NAND gates, interconnected by switching circuits such as transistors. The switching transistors are enabled and disabled as necessary to achieve the desired logic function.
The FPGA must be programmed to enable and disable the interconnecting switching transistors and configure the logic array according to the desired function. In the prior art, some FPGAs have an internal EPROM where each data bit enables or disables one switching transistor in the array. The approach of having an EPROM disposed on each FPGA is expensive and consumes a large space on the IC die.
Another prior art technique uses a single EPROM and passes data and address signals to each FPGA on the printed circuit board. The data bus (8 lines) and address bus (17 lines) metal structure from the EPROM must be routed to many areas of the printed circuit board to configure each FPGA IC. Routing 25 bus lines consumes a large amount of printed circuit board space. Alternately, U.S. Pat. No. 4,870,302 discloses one EPROM that sends parallel data to a master configurable logic array (CLA). The master CLA configures itself and then passes configuration data serially to a first slave CLA. Once the first slave CLA is configured, the first slave CLA passes the serial data along to a second slave CLA, and so on. Thus, fewer data and control lines need be routed around the printed circuit board for configuration. Unfortunately, the master/slave approach tends to complicate the configuration logic and may require synchronization between the master CLA and slave CLAs.
Hence, a need exists to simplify the configuration of FPGAs while using a single data line.